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internally trimmed integrated circuit multiplier ad532 rev. d information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent o r patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2001 C 2011 analog devices, inc. all rights reserved. features pretrimmed to 1.0% (ad532k) no e xternal c omponents r equired guaranteed 1.0% max imum 4 - q uadrant e rror (ad532k) diff erential inputs for (x 1 ? x 2 ) (y 1 ? y 2 )/10 v t ransfer f unction monolithic c onstruction, l ow c ost applications multiplication, d ivis ion, s quaring, s quare r ooting algebraic c omputation power m easurements instrumentation a pplications available in c hip f orm functional block dia gram (with z tied to output) v x v y x 1 x 2 y 1 y 2 r r z output v os 10r r v out = (x 1 ? x 2 ) (y 1 ? y 2 ) 10v 00502-003 x figure 1. general description the ad532 is the first pretrimmed single chip mon olithic mult iplier/ divider. it guarantees a maximum multiplying error of 1.0% and a 10 v output voltage without the need for any external trimming resistors or output op amp. because the ad532 is internally trimmed, its simplicity of use provides design engineers with an attractive alternative to modular multipliers, and its monolithic construction provides significant advantages in size, reliability and economy. further, the ad532 can be used as a direct replacement for other ic multipliers that require external trim networks. f lexibility of o peration the ad532 multiplies in four quadrants with a transfer function of (x 1 ? x 2 )(y 1 ? y 2 )/10 v, divides in two quadrants with a 10 v z/(x 1 ? x 2 ) transfer function, and square roots in one quadrant with a transfer function of 10 v z . in addition to these basic functions, the differential x and y inputs provide significant operating flexibility both for algebraic computation and transducer instrumentation applications. transfer functions, such as xy/10 v , (x 2 ? y 2 ) / 1 0 v, x 2 /10 v, and 10 v z/(x 1 ? x 2 ), are easily atta ined and are extremely useful in many modulati on and function generation applications, as well as in trigonometric calculations for airborne navigation and guidance applications, where the monolithic construction and small size of the ad532 offer considerable system advantages. in addition, the high c mrr (75 db) of the differential inputs makes the ad532 especially well qualified for instrumentation applications, as it can provide an output signal that is the product of two transducer generated input signals. g uaranteed p erformance o ver t emperature th e ad532j and ad532k are specified for maximum multiplying errors of 2% and 1% of full scale, respectively at 25c, and are rated for operation from 0c to 70c. the ad532s has a maximum multiplying error of 1% of full scale at 25c; it is also 100% test ed to guarantee a maximum error of 4% at the extended operating temperature limits of ? 55c and +125c. all devices are available in either the hermetically - sealed to - 100 metal can, to - 116 ceramic dip or lcc packages. the j, k, and s grade chips are also available. a dvantages of on - the - chip t rimming of t he m onolithic ad532 1. true ratiometric trim for improved power supply rejection. 2. reduced power requirements since no networks across supplies are required. 3. more reliable because standard monolithic assembly tec hniques can be used rather than more complex hybrid approaches. 4. high impedance x and y inputs with negligible circuit loading. 5. differential x and y inputs for noise rejection and addit ional computational flexibility.
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ad532 rev. d | page 2 of 16 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 flexibility of operation ................................................................ 1 guaranteed performance over temperature ........................... 1 advantages of on - the - chip trim ming of the monolithic ad532 ............................................................................................ 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 thermal resistance .......................................................................... 5 chip dimensions and bonding diagram ................................ 5 esd caution .................................................................................. 5 pin configuration and function descriptions ............................. 6 typical performance characteristics ............................................. 8 functional description .................................................................. 10 ad532 performance characteristics ........................................... 11 nonlinearity ................................................................................ 11 ac feedthrough ......................................................................... 11 common - mode rejection ........................................................ 11 dynamic characteristics ........................................................... 11 power suppl y considerations ................................................... 11 noise characteristics ................................................................. 11 applications ..................................................................................... 12 rep lacing other ic multipliers ................................................ 12 square root ................................................................................. 13 difference of squares ................................................................. 13 outline dimensions ....................................................................... 14 ordering guide .......................................................................... 15 revision history 2 /1 1 rev. c to rev. d updated format .................................................................. universal added pin configuration and function descriptio ns s e ction ................................................................................................ 6 added typical performance characteristics section .................. 8 changes to figure 11 ........................................................................ 8 changes to figure 12 and figure 13 ............................................... 9 changes to ordering guide .......................................................... 1 5
ad532 rev. d | page 3 of 16 specifications at 25 c, v s = 15 v, r 2 k ? v os gr ounded, unless otherwise noted. table 1 . ad532j ad532k ad532s model conditions min typ max min typ max min typ max unit multiplier performance transfer function v y y x x 10 ) ( ) ( 2 1 2 1 ? ? v y y x x 10 ) ( ) ( 2 1 2 1 ? ? v y y x x 10 ) ( ) ( 2 1 2 1 ? ? total error C 10 v x, y +10 v 1.5 2.0 0.7 1.0 0.5 1.0 % t a = min imum to max imum 2.5 1.5 4.0 % total error vs. temperature 0.04 0.03 0.01 0.04 %/c supply rejection 15 v 10% 0.05 0.05 0.05 %/% nonlinearity, x x = 20 v p - p, y = 10 v 0.8 0.5 0.5 % nonlinearity, y y = 20 v p - p, x = 10 v 0.3 0.2 0.2 % feedthrough, x y n ulled, x = 20 v p - p 50 hz 50 200 30 100 30 100 mv feedthrough, y (x nulled, 30 150 25 80 25 80 mv y = 20 v p - p 50 hz) feedthrough vs. temperature 2.0 1.0 1.0 mv p - p/c feedthrough vs. power supply 0.25 0.25 0.25 mv/% dynamics small signal bw v out = 0.1 rms 1 1 1 mhz 1% amplitude error 75 75 75 khz slew rate v out 20 p - p 45 45 45 v/s settling time to 2%, v out = 20 v 1 1 1 s noise wideband noise 0.6 0.6 0.6 mv (rms) f = 5 hz to 10 khz f = 5 hz to 5 mhz 3.0 3.0 3.0 mv (rms) output v oltage swing 10 13 10 13 10 13 v impedance f 1 khz 1 1 1 ? offset voltage 40 30 30 mv offset voltage vs. temperature 0.7 0.7 2.0 mv/c offset voltage vs. supply 2.5 2.5 2.5 mv/% inp ut amplifiers (x, y, and z) signal voltage range diff erential or cm o perating d iff erential 10 10 10 v cmrr 40 50 50 db input bias current x, y inputs 3 1.5 4 1.5 4 a x, y inputs t min to t max 10 8 8 15 a z input 10 5 15 5 a z input t min to t max 30 25 25 a offset current 0.3 0.1 0.1 a differential resistance 10 10 10 m? divider performance transfer function x l > x 2 10 v z/(x 1 ? x 2 ) 10 v z/(x 1 ? x 2 ) 10 v z/(x 1 ? x 2 ) total error v x = ?10 v, ?10 v v z +10 v 2 1 1 % v x = ? 1 v, ? 10 v v z +10 v 4 3 3 %
ad532 rev. d | page 4 of 16 ad532j ad532k ad532s model conditions min typ max min typ max min typ max unit square performance v x x 10 ) ( 2 2 1 ? v x x 10 ) ( 2 2 1 ? v x x 10 ) ( 2 2 1 ? transfer func tion total error 0.8 0.4 0.4 % square rooter performance transfer function ? 10 v z ? 10 v z ? 10 v z total error 0 v v z 10 v 1.5 1.0 1.0 % power supply specifications supply voltage rated performance 15 15 15 v operating 10 18 10 18 10 22 v supply current quiescent 4 6 4 6 4 6 ma
ad532 rev. d | page 5 of 16 thermal resistance ja is specified for the worst - cas e conditions, that is, a device soldered in a circuit board for surface - mount packages. table 2 . thermal resistance package type ja jc unit h -10a 150 25 c/w e -20a 85 22 c/w d -14 85 22 c/w c hip dimensions a nd b onding d iagr am contact factory for latest dimensions. dimensions are shown in inches and (mm). 0.062 (1.575) gnd z 0.107 (2.718) ?v s +v s y 1 y 2 x 2 x 1 v os output 00502-002 figure 2. esd caution
ad532 rev. d | page 6 of 16 pin configuration and fu nction descriptions y 1 y 2 v os gnd x 2 x 1 ?v s out z +v s ad532 top view (not to scale) 00502-103 figure 3. 10-lead header pin configuration (h-10) 20 19 1 2 3 18 14 15 16 17 4 5 6 7 8 9 10111213 nc = no connect. do not connect to this pin. ?v s y 2 out nc nc nc nc v os nc nc nc gnd z x 1 nc nc +v s nc y 1 x 2 ad532 top view (not to scale) 00502-104 figure 4. 20-lead leadless chip carrier pin configuration (e-20a) 14 13 12 11 10 9 8 1 2 3 4 5 6 7 z+ v s out y 1 ?v s y 2 nc v os nc gnd nc x 2 x 1 nc nc = no connect. do not connect to this pin. ad532 top view (not to scale) 00502-105 figure 5. 14-lead side braize dip (d-14) table 3. 10 lead header pin function descriptions pin no. mnemonic description 1 y 1 y multiplicand input 1 2 +v s positive supply voltage 3 z dual purpose input 4 out product output 5 ?v s negative supply voltage 6 x 1 x multiplicand input 1 7 x 2 x multiplicand input 2 8 gnd common 9 v os output offset adjust 10 y 2 y multiplicand input 2
ad532 rev. d | page 7 of 16 table 4. 20 lead leadless chip ca rrier pin function descriptions pin no. mnemonic description 2 z dual purpose input 3 out product output 4 ?v s negative supply voltage 1, 5, 6, 7, 8, 9, 11, 12, 15, 17 nc no connection 10 x 1 x multiplicand input 1 13 x 2 x multiplicand input 2 14 gnd common 16 v os output offset adjust 18 y 2 y multiplicand input 2 19 y 1 y multiplicand input 1 20 +v s positive supply voltage table 5. 14 lead side braize dip pin function descriptions pin no. mnemonic description 1 z dual purpose input 2 out product output 3 ?v s negative supply voltage 4, 5, 6 nc no connection 7 x 1 x multiplicand input 1 9 x 2 x multiplicand input 2 10 gnd common 11 v os output offset adjust 12 y 2 y multiplicand input 2 13 y 1 y multiplicand input 1 14 +v s positive supply voltage
ad532 rev. d | page 8 of 16 typical performance characteristics 1 0.1 0.01 014 1312 1110 987654321 distortion (%) peak signal amplitude (v) x in y in 00502-005 figure 6. distortion vs. peak signal amplitude 100 1 10 0.1 10 1m 100k 10k 1k 100 distortion (%) frequency (hz) 20v p-p signal x in y in 00502-006 figure 7. distorti on vs. frequency 1k 10 100 1 100 10m 1m 100k 10k 1k feedthrough (mv) frequency (hz) y feedthrough x feedthrough 00502-007 figure 8. feedthrough vs. frequency 70 60 50 40 30 20 10 0 100 10m 1m 100k 10k 1k cmrr (db) frequency (hz) y common-mode rej (x 1 ? x 2 ) = +10v x common-mode rej (y 1 ? y 2 ) = +10v 00502-008 figure 9. cmrr vs. frequency 1 0.1 0.01 10k 10m 1m 100k amplitude (v) frequency (hz) r l = 2k ? , c l = 1000pf r l = 2k ? , c l = 0pf 00502-009 figure 10. frequency response, multiplying 10 1 0.1 10k 10m 1m 100k amplitude (v) frequency (hz) v z = 0.1 v x sin t v x = 1v v x = 5v v x = 10v 00502-010 figure 11. frequency response, dividing
ad532 rev. d | page 9 of 16 4 6 8 10 14 12 10 22 20 18 16 14 12 peak signal voltage (v) power supply voltage (v) saturated output swing max x or y input for 1% linearity 00502-011 figure 12 . signal swing vs. supply 5 0 1 2 3 4 10 100k 10k 1k 100 spot noise (v/ hz) frequency (hz) 00502-012 figure 13 . spot noise vs. frequency
ad532 rev. d | page 10 of 16 f unctional d escription the functional block diagram for the ad532 is shown in figure 1 and the complete schematic in figure 14 . in the multiplying and squaring modes, z is connected to the output to close the feedback around the output op amp. in the divide mode, it is used as an input terminal. the x and y inputs are fed to high impedance differential amplifiers featuring low distortion and good com mon - mode rejection. the amplifier voltage offsets are actively laser tri mmed to zero during production. the product of the two inputs is resolved in the multiplier cell using gilberts linearized transconductance technique. the cell is laser trimmed to obt ain v out = (x 1 ? x 2 )(y 1 ? y 2 )/10 volts. the built - in op amp is used to obtain low output impedance and make possible self - contained operation. the residual output voltage offset can be zeroed at v os in critical applications. o therwise , the v os pin should be gro unded. x 2 x 1 y 1 com r2 r34 r9 r1 q1 q2 q3 q4 q5 q6 r3 r6 r8 r16 q7 q8 q14 q15 q9 q10 r13 y 2 r18 r4 r5 r10 r32 q28 q11 q12 r11 r19 r14 r12 r15 q13 q16 q17 r23 r20 r22 r21 c1 q21 r27 q2 5 z r33 v os output r30 r28 r29 r31 q26 q27 q22 q23 q24 r26 r25 r24 q20 q19 q18 +v s ?v s can 00502-004 figure 14 . schematic diagram
ad532 rev. d | page 11 of 16 ad532 p erformance c haracteristics multiplication accuracy is defined in terms of total error at 25c with the rated power supply. the value specified is in percent of full scale and includes x in and y in nonlinearities, feedback and scale factor error. to this must be added such application - dependent error terms as power supply rejection, common - mode rejection and temperature coefficients (although worst case error over temperature is specified for the ad532s). total expected error is the rms sum of the individual components because they are uncorrelated. accuracy in the divide mode is only a little more complex. to achieve division, the multiplier cell must be connected in the feedback of the outpu t op amp as shown in figure 17 . in this configuration, the multiplier cell varies the closed loop gain of the op amp in an inverse relationship to the denominator voltage . therefore , as the denominator is reduced, output offset, b and - width , and other multiplier cell errors are adversely affected. the divide error and drift are then m 10 v/x 1 ? x 2 ) where m represents multiplier full - scale error and drift, and (x 1 ? x 2 ) is the absolute value of the denominator. n onlinearity nonli nearity is easily measured in percent harmonic distortion. t he curves of figure 6 and figure 7 characterize output disto rtion as a function of input signal level and frequency respectively, with one input held at plus or minus 10 v dc. in figure 7 , the sine wave amplitude is 20 v (p - p). ac f eedthrough ac feedthrough is a measure of the multipliers zero suppression . with one input at zero, the multiplier output should be zero rega rdless of the signal applied to the other input. feedthrough as a function of frequency for the ad532 is shown in figure 8 . it is measured for the condition v x = 0, v y = 20 v (p - p) and v y = 0, v x = 20 v (p - p) over the given frequ ency range. it consists primarily of the second harmonic and is measured in millivolts peak - to - peak. c ommon - m ode r ejection the ad532 features differential x and y inputs to enhance its flexibility as a computational multiplier/divider. common - mode rejecti on for both inputs as a function of frequency is shown in figure 9 . it is measured with x 1 = x 2 = 20 v (p - p), (y 1 ? y 2 ) = 10 v dc and y 1 = y 2 = 20 v (p - p), (x 1 ? x 2 ) = 10 v dc. d ynamic c haracteristics the closed loop frequency re sponse of the ad532 in the multiplier mode typically exhibits a 3 db bandwidth of 1 mhz and rolls off at 6 db/octave , thereafter. response through all inputs is essentially the same as shown in figure 10 . in the divide mode, the closed loop frequency response is a function of the absolute value of the denominator voltage as shown in figure 11. stable operation is maintained with capacitive loads to 1000 pf in all modes, except the square root for which 50 pf is a safe upper limit. higher capacitive loads can be driven if a 100 resistor is connected in series with the output for isolation. p ower s upply c onsiderations although the ad532 is tested and specified with 15 v dc supplies , it may be operated at any supply voltage from 10 v to 18 v for the j and k versions, and 10 v to 22 v for the s version. the input and output signals must be reduced proportionately to prevent saturation; however, with supply voltages below 15 v , as shown in figure 12. because power supply sensitivity is not dependent on external null networks as in other conventionally nulled multipliers, the power supply rejection ratios are improved from 3 to 40 times in the ad532. n oise c haracteristics all ad53 2s are screened on a sampling basis to assure that output noise will have no appreciable effect on accuracy. typical spot noise vs. frequency is shown in figure 13.
ad532 rev. d | page 12 of 16 a pplications the performance and ease of use of the ad532 i s achieved through the laser trimming of thin - film resistors deposited directly on the monolithic chip. this trimming - on - the - chip technique provides a number of significant advantages in terms of cost, reliability and flexibility over conventional in - packa ge trimming of off - the - chip resistors mounted or deposited on a hybrid substrate. first and foremost, trimming on the chip eliminates the need for a hybrid substrate and the additional bonding wires that are required between the resistors and the multiplie r chip. by trimming more appropriate resistors on the ad532 chip itself, the second input terminals that were once committed to external trimming networks have been freed to allow fully differential operation at both the x and y inputs. further, the requir ement for an input attenuator to adjust the gain at the y input has been eliminated, letting the user take full advantage of the high input impedance properties of the input differential amplifiers. therefore, the ad532 offers greater flexibility for both algebraic computation and transducer instrumentation applications. finally, provision for fine trimming the output voltage offset has been included. this connection is optional, however, as the ad532 has been factory - trimmed for total performance as descri bed in the listed specifications. r eplacing o ther ic m ultipliers existing designs using ic multipliers that require external trimming networks can be simplified using the pin - for - pin replaceability of the ad532 by merely grounding the x 2 , y 2 and v os termin als. the v os terminal should always be grounded when unused. multiplication z out ad532 x 1 x 2 y 1 y 2 v out v os 20k? +v s ?v s v out = (x 1 ? x 2 ) (y 1 ? y 2 ) 10v (optional) 00502-013 figure 15 . multiplier connection for operation as a multiplier, the ad532 should be connected as shown in figure 15 . the inputs can be fed differentially to the x and y inputs, or single - ended by simply grounding the unused input. connect the inputs according to the desired polarity in the output. the z terminal is tied to the output to close the feedback loop around the op amp (s ee figure 1 ). the offset adjust v os is optional and is adjusted when both inputs are zero volts to obtain zero out, or to buck out other system offsets. s quaring ad532 x 1 x 2 y 1 y 2 v out 20k? +v s ?v s +v s ?v s v os v out = v in 2 10v (optional) z out v in 00502-014 figure 16 . squarer connection the squaring circuit in figure 16 is a simple variation of the multiplier. the differential input capability of the ad532, however, can be used to obtain a positive or negative output response to the input, a useful feature for co ntrol applications , as it might eliminate the need for an additional inverter somewhere else. d ivision ad532 20k? (x 0 ) 47k? 2.2k? 10k? 1k? (sf) +v s ?v s +v s ?v s v out = 10vz x z out z v out x x 1 x 2 y 1 y 2 00502-015 figure 17 . divider connection the ad532 can be configured as a two - quadrant divider by connecting the multiplier cell in the feedback loop of the op amp and using the z terminal as a signal input, as shown in figure 17 . it should be noted, however, that the output error is given approximately by 10 v m /(x 1 ? x 2 ), where m is the total error specificati on for the multiply mode; and bandwidth by f m (x 1 ? x 2 )/10 v, where fm is the bandwidth of the multiplier. further, to avoid positive feedback, the x input is restricted to negative values. thus , for single - ended negative inputs (0 v to ? 10 v), connect the input to x and the offset null to x 2 ; for single - ended positive inputs (0 v to +10 v), connect the input to x 2 and the offset null to x1. for optimum performance, gain (s.f.) and offset (x 0 ) adjustments are recommended as shown and explained in table 6 . for practical reasons, the useful range in denominator input is approximately 500 mv |(x 1 ? x 2 )| 10 v. the voltage offset adjust (v os ), if used, is trimmed with z at zero and (x 1 ? x 2 ) at full scale.
ad532 rev. d | page 13 of 16 table 6 . adjust ment procedu re (divider or square rooter) d ivider s quare r ooter with: adjust for: with : adjust : for: adjust x z v out z v out scale factor ? 10 v +10 v ? 10 v +10 v ? 10 v x 0 (offset) ? 1 v +0.1 v ? 1 v +0.1 v ? 1 v repeat if required. s quare r oot ad532 20k? (x 0 ) 47k? 2.2k? 10k? 1k? (sf) +v s ?v s +v s ?v s v out = 10vz z out z v out x 1 x 2 y 1 y 2 00502-016 figure 18 . square rooter connection the connections for square root mode are shown in figure 18. similar to the divide mode, the multiplier cell is connected in the feedback of the op amp by connecting t he output back to both the x and y inputs. the diode d 1 is connected as shown to prevent latch - up as z in approaches 0 volts. in this case, the v os adjustment is made with z in = +0.1 v dc, adjusting v os to obtain ? 1.0 v dc in the output, v out = ? 10 v z . for optimum performance, gain (s.f.) and offset (x 0 ) adjustments are recom - mended as shown and explained in table 6 . d ifference of s quares ad532 20k? +v s ?v s +v s ?v s v os v out x 1 x 2 y 1 y 2 z out 20k? 20k? 10k? ?y x y (optional) v out = x 2 ? y 2 10v ad741kh 00502-017 figure 19 . differential of squares connection the differential input capability of the ad532 allows for the algebraic solution of several interesting functions, such as the difference of squares, x 2 ? y 2 /10 v. as shown in figure 19, t he ad532 is configured in the square mode, with a simple unity gain inverter connected between one of the signal inputs (y) and one of the inverting input terminals ( ? y in ) of the multiplier . the inverter should use precision (0.1%) resistors or be otherwis e trimmed for unity gain for best accuracy.
ad532 rev. d | page 14 of 16 outline dimensions c ontrolling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents fo r reference only and are not appropriate for use in design . 14 1 7 8 0.310 (7.87) 0.220 (5.59) pin 1 0.080 (2.03) max 0.005 (0.13) min seating plane 0.023 (0.58) 0.014 (0.36) 0.060 (1.52) 0.015 (0.38) 0.200 (5.08) max 0.200 (5.08) 0.125 (3.18) 0.070 (1.78) 0.030 (0.76) 0.100 (2.54) bsc 0.150 (3.81) min 0.765 (19.43) max 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) figure 20. 14-lead side-brazed cera mic dual in-line package [sbdip] (d-14) dimensions shown in inches and (millimeters) controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. 1 20 4 9 8 13 19 14 3 18 bottom view 0.028 (0.71) 0.022 (0.56) 45 typ 0.015 (0.38) min 0.055 (1.40) 0.045 (1.14) 0.050 (1.27) bsc 0.075 (1.91) ref 0.011 (0.28) 0.007 (0.18) r typ 0.095 (2.41) 0.075 (1.90) 0.100 (2.54) ref 0.200 (5.08) ref 0.150 (3.81) bsc 0.075 (1.91) ref 0.358 (9.09) 0.342 (8.69) sq 0.358 (9.09) max sq 0.100 (2.54) 0.064 (1.63) 0.088 (2.24) 0.054 (1.37) 022106-a figure 21. 20-terminal cerami c leadless chip carrier [lcc] (e-20-1) dimensions shown in inches and (millimeters) controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. dimensions per jedec standards mo-006-af 0.500 (12.70) min 0.185 (4.70) 0.165 (4.19) reference plane 0.050 (1.27) max 0.040 (1.02) max 0.335 (8.51) 0.305 (7.75) 0.370 (9.40) 0.335 (8.51) 0.021 (0.53) 0.016 (0.40) 1 0.034 (0.86) 0.025 (0.64) 0.045 (1.14) 0.025 (0.65) 0.160 (4.06) 0.110 (2.79) 6 2 8 7 5 4 3 0.115 (2.92) bsc 9 10 0.230 (5.84) bsc base & seating plane 36 bsc 022306-a figure 22. 10-pin metal header package [to-100] (h-10) dimensions shown in inches and (millimeters)
ad532 rev. d | page 15 of 16 ordering guide model 1 temper ature range package description package option ad532jchips 0c to 70c chip ad532jd 0c to 70c 14- lead sbdip d -14 ad 532jdz 0c to 70c 14- lead sbdip d -14 ad532jh 0c to 70c 10- pin metal header package [to -100] h -10 ad532jhz 0c to 70c 10- pin metal header package [to -100] h -10 ad532kd 0c to 70c 14- lead sbdip d -14 ad532kdz 0c to 70c 14- lead sbdip d -14 ad532kh 0c to 70c 10- pin metal header package [to -100] h -10 ad532khz 0c to 70c 10- pin metal header package [to -100] h -10 ad532schips ? 55c to +125c chip ad532sd ? 55c to +125c 14- lead sbdip d -14 ad532sd/883b ? 55c to +125c 14- lead sbdip d -14 ad532se/883b ? 55c to +125c 20- terminal lcc e -20-1 ad532sh ? 55c to +125c 10- pin metal header package [to -100] h -10 ad532sh/883b ? 55c t o +125c 10- pin metal header package [to -100] h -10 1 z = rohs compliant part.
ad532 rev. d | page 16 of 16 notes ? 2001 C 2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d00502 - 0 - 2/11(d)

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